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So, what could be achieved? I labored out a hybrid technique the place I send data utilizing CPU writes and receive using DMA. This labored for two channels, however wouldn’t work for extra. As soon as I received rev2 boards that had 4 RAM chips, even this failed, as simply the 4 obtain DMA units starved one another of bandwidth and bought cancelled. Why was Atmel so rattling stingy with inside SRAM? We’ll probably never know. But they could have solved this exact difficulty easier than with 192 bytes of SRAM within the DMA unit. Just adding a 4-byte FIFOs into the SPI models would do as well, then every DMA transaction may transfer greater than a single byte, alleviating this traffic jam. Sadly, apparently no person at Atmel has even tried to truly use their chip for anything. Atmel, what occurred to you?
